LIBRARY ieee;
USE ieee.std_logic_1164.all;

PACKAGE components IS

	COMPONENT regn -- register
		GENERIC (N : INTEGER := 8);
		PORT ( R			: IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
			   Rin, Clock	: IN		STD_LOGIC;
			   Q			: OUT		STD_LOGIC_VECTOR(N-1 DOWNTO 0) );
	END COMPONENT;
	
	COMPONENT fulladder -- full adder
		PORT(Cin, x , y		: IN STD_LOGIC;
			 s,Cout			: OUT STD_LOGIC);
	END COMPONENT;
	
	COMPONENT trin -- tri-state buffer
		GENERIC (N : INTEGER := 8);
		PORT ( X	: IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
			   E	: IN		STD_LOGIC;
			   F	: OUT		STD_LOGIC_VECTOR(N-1 DOWNTO 0) );
	END COMPONENT;

	-- unidade de controle
	COMPONENT controlunit
		PORT(instruction : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
			 WB, MEM     : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
			 EX 		 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT;
	
	COMPONENT ula IS
		PORT( Op				: IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
			  X, Y				: IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
			  S					: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
			  Cout				: OUT STD_LOGIC;
			  Overflow			: OUT STD_LOGIC);
	END COMPONENT;
	
	COMPONENT adder IS
	PORT(currAdd :IN STD_LOGIC_VECTOR (7 DOWNTO 0) ;
		 nextAdd :OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
	END COMPONENT;
			
	COMPONENT upcount -- two-bit up-counter with synchronous reset
		PORT ( Clear, Clock	: IN		STD_LOGIC;
			   Q			: BUFFER	STD_LOGIC_VECTOR(2 DOWNTO 0) );
	END COMPONENT;
	
	COMPONENT inst_mem IS
		PORT ( Address		: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			   Instruction	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
			   Immediate 	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT;
	
	COMPONENT registers IS
		PORT (  Instr				: IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
				R1, R2, R3, R4		: IN 	STD_LOGIC_VECTOR(7 DOWNTO 0);
				Imed				: IN 	STD_LOGIC_VECTOR(7 DOWNTO 0);
				R1Out, R2Out		: OUT 	STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT;
	
	COMPONENT ulaDecoder IS
		PORT (  Instr				: IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
				Op					: OUT 	STD_LOGIC_VECTOR(1 DOWNTO 0));
	END COMPONENT;
	
	COMPONENT fetch IS
		PORT (  Tick				: IN	STD_LOGIC_VECTOR(2 DOWNTO 0);
				Clock				: IN	STD_LOGIC;
				--nextAddressWire     : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
				Instr				: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
				Immed				: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT;


END components;